In this paper after studying and analyzing BiCMOS and CMOS logical gates, we have achieved some advanced BiCMOS circuits for the same logical gates. In all of our designs, we used threshold detectors and voltage to current converters. In this new method, some parts of the conventional BiCMOS current-mode circuits have been eliminated without any changes in the logical functionality of the circuits, and some optimum circuits based on this logic family have been introduced. In the proposed circuits, we have obtained considerable speed gain and a remarkable reduction in transistor count.      

In this paper the design of new high-speed current mode BiCMOS logic circuits is proposed. By altering the threshold detector circuit of the conventional current mode logic circuits and applying the multiple value logic (MVL) approach the number of transistors in basic logic operators are significantly reduced and hence a reduction of chip area and power dissipation as well as an increase in speed is achieved. Simulation with HSpice using BSIM 3V3 model and experimental 65nm BiCMOS technology were carried out for speed, and power consumption considerations at different supply voltage levels. Finally the performance of the proposed circuit is compared to an 8 bit voltage mode adder.

This paper introduces four new resistorless circuits of first-order current-mode all-pass filter (CMAPF) based on dual-X current conveyor transconductance amplifier (DXCCTA). All the four circuits use a single DXCCTA and a capacitor for their realization. The main features of the proposed CMAPFs are: use of minimum active and passive components, resistorless realization, electronically adjustable pole frequency, easily cascadable, good sensitivity performance with respect to active and passive elements, low total harmonic distortion of output current (0. 74%) and good operating frequency range (39. 2 MHz). The non-ideal analysis of the proposed circuits has also been explored. Moreover, two applications of the proposed first-order CMAPF in terms of second order CMAPF and current-mode quadrature oscillator are also presented. HSPICE simulations have been carried out with 0. 18 μ m CMOS process parameters to validate the proposed circuits.

The goal of this research is designing an analog current-mode time-delay cell based on a current-mode first-order all-pass filter with high output impedance. The proposed all-pass filter as a time-delay cell consists of a class AB cascode current mirror and also a differential input voltage current conveyor (DVCC) as an active element employing only two grounded passive components for phase shifting and required time delay. The proposed time-delay cell is capable of working at low-voltage headroom and has high speed operation and a low-power consumption of 1. 39mW. The value of delay can be controlled by both fine-tuning and coarse-tuning. This time-delay cell can generate a delay of 14ns while it is able to reach a minimum delay of 6ns across a 100MHz bandwidth by using fine-tuning and coarse-tuning of the time-delay cell, as well. The proposed cell can be used in the beamforming, radars, and medical engineering. HSPICE simulations are performed based on a 0. 18µ m standard CMOS technology.

This paper proposes a new modified adaptive sliding mode controller in order to control the inverters of DGS in the voltage and current (power) control modes in a microgrid. An observer is used to estimate the uncertain parameters in controller design and considering these estimated values, the controller is adapted to new condition. In the power management strategy, one of inverter controls the voltage and the other inverter controls the load current and balances the active power. Due to delays in startup power electronic converter and sliding mode controller, the result of controller implementation with classical controllers does not meet the requirement and so, considering these delays with adaptive controller, the performance will be improved considerably and the reference signal will be tracked with lower steady state error in comparison with classical sliding mode controller. Moreover, this controller reduces the total harmonic distortion and improves the rms and peak value tracking. Implementation of system using DSP/TMS320F28335 as well as MATLAB simulation validates the performance of system in different conditions.

In this paper a new synthesis for circuit design of Euclidean distance calculation is presented. The circuit is implemented based on a simple two-quadrant squarer/divider block. The circuit that employs floating gate MOS (FG-MOS) transistors operating in weak inversion region, features low circuit complexity, low power (<20uW), low supply voltage (0.5V), two quadrant input current, wide dynamic range and immunity from body effect. In addition, this circuit is designed in modular methodology, leading to a very regular structure. The circuit was successfully applied to the recognition of some simple patterns. Simulation results of the circuit by HSPICE show high performance in the separation and confirm the validity of the proposed technique.

The relationship between the amount of energy consumption and the circuit speed to change the design efficiency is an important challenge in designing digital circuits. Adders are essential components of computing circuits that play an important role in computing speed. This article proposed a new design for a single-bit current mode full adder using the field effect transistors based on carbon nanotubes to enhance the speed and reduce the occupied space on the chip. The correct combination of the majority function, the current mirror technique, and the sum value on carry reduced the delay of all adder circuits. The simulations have been done by HSPICE software and based on the provided standard model of 32 nm with CNTFET technology. The proposed design has improved by 55% in terms of delay. The PDP level in the proposed design has decreased by 63% compared to the previous designs.

 In this paper a new structure for the MLF (Multi Loop Feedback) Gm-C group of filters is presented, granting the advantages of both current-mode and fully balanced topologies to the conventional structure of the group. The ability of the structure to perform even more transfer functions (Low pass and Band Pass) than other members of the group is proved. Methods of enabling the proposed structure to perform other popular transfer functions are also presented. The favorite feature of systematical generation of the structure facilitates its arrangement for any order. For practical comparison, a Butterworth 4th–order LP filter with a cut-off frequency of 10MHz is designed in three different structures viz; the proposed one, the single-ended current mode, and fully balanced voltage mode. Simulation results show that the PSRR+,PSRR-,CMRR, Noise, THD, DR, consumed power (P) and Figure of Merit (FOM) of the new structure compared to its voltage mode counterpart are improved at least by factors of 36643, 59841, 4.75, 76, 2, 2.45, 1.17 and 509500, respectively. Compared to single ended current-mode type they are improved by factors of 40, 73, not defined, 1.3, 7.8, 150, 0.68 and 1763000, respectively. Although the above mentioned comparison, due to both the similarity of the used technology and the completeness of the results, is the most equitable one for the most definite conclusion, to further widen the extent of the comparison, the proposed structure is also compared with some other works yet assumed as its closet counterparts. This latter comparison also proves the certain superiorities of the proposed structure such that its FOM is from 8500 to 4512740 times larger than those of others. Closer tracking of the input signal at pass-band and more attenuation at stop-band are also achieved by this structure. These results strongly support the theoretical suggestions. Most favorably the much higher PSRR of the new structure makes it an extremely suitable choice for Mix-Mode (System-On- a Chip, SOC/SOI) applications where power supplies (and analog blocks) suffer severely from digital noise.